Principal ASIC Design & Verification Engineer

Seniority LevelEmployment TypeJob Functions

What if the devices you use every day were smart enough to understand their environment and your intent? Imagine what’s possible when your camera can accurately perceive what it’s seeing and hearing without compromising your privacy. Imagine if your appliances knew exactly what to do. No complicated settings, just perfect results. So simple it feels like magic. Join the dynamic and experienced team at Perceive, which is making magic a reality, as a Principal ASIC Design & Verification Engineer. Be part of the team that’s transforming sensing into perceiving! 

Job Description Summary

Perceive is seeking a Principal ASIC Design and Verification Engineer to join our highly-skilled ASIC development team. The ideal candidate is deeply experienced in the design and verification of complex SoCs.  She/he will work closely as a member of the Perceive ASIC Hardware team in designing and verifying industry-leading edge computing solutions. The candidate should be self-motivated and focused, comfortable collaborating with geographically dispersed teams, passionate about all aspects of ASIC development, driven by team success, and eager to make a difference in a start-up environment.

Essential Duties and Responsibilities

  • Define, implement and verify different aspects of ASIC development – block-level, subsystem, and full-chip
  • Design and integrate IP and verification collateral into SoCs
  • Collaborate with the architecture, software and hardware teams to ensure successful implementation and verification of SoCs
  • Maintain, manage, and evolve design & verification infrastructure and methodologies distributed across the development teams
  • Develop verification environments with a strong focus on efficiency, stability, scalability and automation
  • Verify various operations and system states of SoC – mission-mode, test-mode, boot sequence, power states, etc.

Required Skills

  • MSc or BSc in Electrical Engineering, Computer Engineering, Computer Science, or related field with at least 7+ years of experience with ASIC development
  • Extensive experience with design implementation tools and metholdologies (RTL coding, low-power implementation, IP integration)
  • Extensive experience with verification simulation and debugging tools, low-power verification, block-level/subsystem/full-chip verification, verification methodologies (assertions, lint, coverage), and general automation
  • Strong coding skills in Verilog HDL design, SystemVerilog (UVM preferred), C/C++, and scripting (Python preferred)
  • Strong understanding of hardware design and computer architecture concepts
  • Ability to generate and verify synthesis constraints
  • Experience with source code management and issue/task tracking
  • Ability to work effectively with both internal and external teams
  • Excellent written and verbal communication skills

Preferred Skills

  • Experience developing imaging and/or audio applications, IoT platforms, embedded system security, and/or machine learning applications
  • Experience with Post-Silicon validation and board level debug
  • Experience with FPGA development and prototyping
  • Experience with formal verification methodologies
  • Experience with synthesis and static timing analysis tools

Work Environment

  • This position involves working mainly in a typical desk/office environment, but it can also involve working in a lab setting
  • Occasional travel to other Perceive or ASIC provider offices may be required


  • Office locations: Boise, Idaho, San Jose, California and Vancouver, British Columbia
  • Remote work supported