Principal ASIC Physical Design Engineer

Seniority LevelEmployment TypeJob Functions

What if the devices you use every day were smart enough to understand both their environment and your intent? Imagine what’s possible when your camera can accurately perceive what it’s seeing and hearing without compromising your privacy. Imagine your wearable devices seamlessly integrating into your life, doing what you need them to do for as long as you need them to do it. Imagine if your appliances knew exactly what to do. No complicated settings, just perfect results. So simple it feels like magic.

Join the dynamic and experienced team at Perceive, which is making magic a reality, as Principal ASIC Physical Design Engineer. Be part of the team that’s transforming sensing into perceiving!

Job Description Summary

Perceive is seeking a Principal ASIC Physical Design Engineer to join our highly-skilled ASIC development team. The ideal candidate is deeply experienced in the design of complex SoCs using RTL to GDS flows. She/he will work closely with other members of Perceive’s ASIC design team and silicon implementation partners to create industry-leading edge computing solutions. The candidate should be self-motivated and focused, comfortable collaborating with geographically dispersed teams, passionate about all aspects of ASIC development, driven by team success, and eager to make a difference in a start-up environment.

Job Responsibilities

  • Guidance and oversight of technical aspects of ASIC provider physical design and DFT activities including top-level floor plan
  • Synthesis and constraints development for top-level and block-level, including both internally developed and third-party IP
  • Ownership of power intent including UPF development, power island/clock gating strategies, and power analysis
  • Timing and physical verification of ASIC provider deliverables, logical equivalency checking
  • ECO implementation and verification
  • Development of physical design tool flows inside Perceive

Required Skills

  • MSc or BSc in Electrical Engineering, Computer Engineering, Computer Science, or related field with at least 10 years of experience with RTL to GDS physical design
  • Hands-on experience of the entire SoC/ASIC design flow including synthesis, floorplanning, CTS, P&R, timing closure, DRC/LVS checks, power analysis, EM & IR analysis using industry standard tools & methodologies
  • Solid experience with physical synthesis, block and full-chip implementation with current industry P&R/STA flows and tools
  • Experience with power intent development (UPF), multi-voltage, power islanding & power intent verification
  • Experience with clock tree synthesis (CTS) of multi-clock designs
  • Experience with static timing analysis (STA) and formal equivalency checks
  • Experience with top and block level floor plan development, implementing power grid and area/congestion optimization
  • Ability to work effectively with both internal and external teams
  • Strong coding skills in Verilog, Tcl, Python and shell scripting
  • Excellent written and verbal communication skills

Preferred Skills

  • Experience with 14/16nm or smaller process nodes is strongly preferred
  • Sign-off experience with reliability, signal integrity, noise, power, physical and DFM

Work Environment

  • This position involves working mainly in a typical desk/office environment, but it can also involve working in a lab setting
  • Occasional travel to other Perceive or ASIC provider offices may be required


  • Preferred locations: San Jose, California or Boise, Idaho
  • Other locations: Vancouver, British Columbia