Senior ASIC Backend Implementation Engineer

Seniority LevelEmployment TypeJob Functions

What if the devices you use every day were smart enough to understand both their environment and your intent? Imagine what’s possible when your camera can accurately perceive what it’s seeing and hearing without compromising your privacy. Imagine your wearable devices seamlessly integrating into your life, doing what you need them to do for as long as you need them to do it. Imagine if your appliances knew exactly what to do. No complicated settings, just perfect results. So simple it feels like magic.

Join the dynamic and experienced team at Perceive, which is making magic a reality, as Senior ASIC Backend Implementation Engineer. Be part of the team that’s transforming sensing into perceiving!

Job Description Summary

Perceive is seeking a Senior ASIC Backend Implementation Engineer to join our highly-skilled ASIC development team. The ideal candidate is deeply experienced in the design of complex SoCs using RTL to GDS flows. She/he will work closely with other members of Perceive’s ASIC design team and silicon implementation partners to create industry-leading edge computing solutions. The candidate should be self-motivated and focused, comfortable collaborating with geographically dispersed teams, passionate about all aspects of ASIC development, interested in machine learning, driven by team success, and eager to make a difference in a start-up environment.

Essential Duties and Responsibilities

  • Synthesis and constraints development for top-level and block-level, including both internally developed and third-party IP
  • Ownership of power intent including UPF development, power island/clock gating strategies, and power analysis
  • Guidance and oversight of technical aspects of ASIC Backend Partner design & integration activities
  • Logical equivalency checking, timing verification and power intent verification of ASIC provider deliverables
  • ECO implementation and verification
  • Development of Backend ASIC tool flows inside Perceive

Minimum Qualifications

  • MSc or BSc in Electrical Engineering, Computer Engineering, Computer Science, or related field with at least 8 years of experience with RTL to GDS Backend design
  • Strong working knowledge of the SoC/ASIC design flow with experience taping out designs
  • Strong experience with synthesis and constraint development at top and block-level with current industry static timing analysis (STA) flows and tools
  • Experience with power intent development (UPF), multi-voltage, power islanding
  • Experience with clock tree synthesis (CTS) of multi-clock designs
  • Experience with logical equivalency checks (LEC), power intent verification, and static timing analysis (STA)
  • Ability to work effectively with both internal and external teams
  • Strong coding skills in Verilog, Tcl, Python, Perl, and shell scripting
  • Unix/Linux literate
  • Excellent written and verbal communication skills

Preferred Qualifications

  • Experience with 14/16FF, 22FDSOI or smaller process nodes is strongly preferred
  • Sign-off experience with signal integrity, noise, power, reliability and DFM

Work Environment

  • This position involves working mainly in a typical desk/office environment, but it can also involve working in a lab setting
  • Occasional travel to other Perceive or ASIC provider offices may be required


  • Preferred locations: San Jose, California or Boise, Idaho
  • Other locations: Vancouver, British Columbia